1. Field
The invention relates generally to the design of semiconductor integrated circuits (ICs). More specifically, the invention relates to a method for ensuring signal integrity in integrated circuits with multiple metal layers, by introducing a secondary power grid for providing additional supply voltage to logic cells with high power consumption within the design.
2. Description of the Related Art
An integrated circuit (IC) is a device which includes a plurality of electronic components (e.g. transistors, resistors, diodes etc.). These components are interconnected to form multiple circuit components (gates, cells, memory units etc.) on the IC. Modern very large scale integration (VLSI) integrated circuits are typically made up of a layer structure with multiple layers of wiring (called “metal layers”) that interconnect its electronic and circuit components. Each metal layer typically has a preferred wiring direction, and the preferred direction alternates between successive metal layers. Many IC designs use the Manhattan wiring model: in each metal layer, all supplies to the IC's electronic and circuit components (i.e. global power supply and global ground) are laid out in a grid of parallel—horizontal or vertical—stripes, and the components connect to these stripes perpendicularly. Designs with multiple metal layers exhibit alternating layers of preferred-direction horizontal and vertical wiring. In a multi-layer design, electrical interconnects (vias) between the metal layers as well as interconnects within the layers allow the IC's components to be connected to the power and ground stripes and to each other, thus completing the circuit.
As part of IC design, logic cells and their connections are defined in terms of a netlist (in a so-called logic synthesis step) and are subsequently placed on the various layers of the chip (in a so-called placement step). Generally, logic cells are cast into standard cells of a predetermined width for vertical circuit rows (or predetermined height for horizontal circuit rows) which are designed and placed in such a way as to align to the power grid stripes on their metal layer; thus, the standard cells residing in a given metal will generally be supplied by the power supply grid of this metal layer.
An important aspect of IC design consists in ensuring signal integrity: If the wire resistance and/or cell current of some cells within the IC exceeds a predetermined limit, voltage drops (aka IR drops) may occur, causing an increase of gate and signal delays and—in the worst case—switching failures of the integrated circuit. Thus, in order to avoid failures caused by signal integrity problems, sufficient electrical power has to be provided to all cells within the integrated circuit.
Various methods of reducing voltage drop in integrated circuits have been suggested:
U.S. Pat. No. 7,240,314 B1 describes a method of introducing metal fill geometries and connecting them to the power mesh using vias or wires at multiple locations. The metal fill geometries thus inserted are electrically connected to the circuit's power mesh structure in a redundant way, thus adding more pathways for current flow between different points of the power mesh. As a consequence, the effective resistance of the power mesh is reduced, resulting in a reduction of voltage drop in the power mesh. An alternate method of implementing metal-fill patterns on integrated circuits, and thus reducing power wiring resistance, is disclosed in U.S. Pat. No. 7,328,419 B2. Note that in both patents the metal fill geometries are introduced after signal wiring, i.e. after completing the layout.
US 2007/0246827 A1 tackles the problem of exceeding power drop within the IC by providing a plurality of first and second power wirings which are confined to different wiring layers and are aligned orthogonal to each other. The plurality of first power wirings and the plurality of second power wirings overlap with each other at a plurality of intersections. Depending on the power requirements of cells fed by the first power wirings, vias are selectively placed on (or removed from) the intersections between the first and second power wirings in an effort to supply sufficient power to all cells within the IC.
U.S. Pat. No. 7,462,941 B2 proposes a design in which the power supply voltages are routed through a mesh of conductive traces which is located in a conducting layer of the integrated circuit and traverses the integrated circuit, e.g. in a diagonal direction. Power is fed to the traces from external voltage sources through a multitude of solder bumps. The traces are designed to provide more direct and more uniform paths to route power supply voltages to the components of the integrated circuit.
U.S. Pat. No. 7,536,658 B2 describes an automated tool (called “power pad synthesizer”) for placing/adding chip power supply pads on the periphery of the IC design as well as in interior locations of the IC design in such a way as to reduce maximum power drops of cells within the IC design. An alternate method for placing power-supply pads and pins in integrated circuit design is discussed in “Optimal Placement of Power-Supply Pads and Pins” by Min Zhao et al., IEEE Transactions of Computer Aided Design of Integrated Circuits and Systems, 2006, p. 144-154. Yet another method for placing power supply pads optimally for a given power network is disclosed in “P/G Pad Placement Optimization: Problem Formulation for Best IR Drop” by Aishwarya Dubey, Proceedings of the 6th Int'l Symposium on Quality Electronic Design, 2005.
US 2008/0066026 A1 describes a tool (called “power network analyzer) for identifying intersections and vias of power wires in an integrated circuit device, estimating conductances of vias and wire segments and estimating currents as well as voltage drops within the design. This tool assists human IC designers in detecting unacceptable power drops and improving the design so as to ensure signal integrity.
Furthermore, “Congestion-Aware Topology Optimization of Structured Power/Ground Networks” by Singh and Sapatnekar, IEEE Transactions of Computer Aided Design of Integrated Circuits and Systems, 2005, p. 683-695, proposes usage of locally regular, globally irregular grids for optimizing the design of power/ground networks and minimizing IR drop across the integrated circuit. The power grid chip area is divided into a set of rectangular tiles connected to each other, and a hierarchical circuit analysis approach is applied to identify the tiles containing nodes with the largest IR drops. Starting from an initial configuration with an equal number of wires in each of the rectangular tiles, wires are added using an iterative sensitivity based optimizer. These additional wires are introduced into the respective tile in such a way that they form a mesh of horizontal and vertical conductors covering the tile.